View CY7C68000A_2287958.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY7C68000A mobl-usb? tx2 usb 2.0 utmi transceiver cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-08052 rev. *g revised october 5, 2008 mobl-usb ? tx2 features utmi-compliant and usb 2.0 ce rtified for device operation operates in both usb 2.0 high speed (hs), 480 mbits/second, and full speed (fs), 12 mbits/second optimized for seamless interface with intel ? monahans appli- cations processors tri-state mode enables sharing of utmi bus with other devices serial-to-parallel and parallel-to-serial conversions 8-bit unidirectional, 8-bit bidirectional, or 16-bit bidirectional external data interface synchronous field and eop detection on receive packets synchronous field and eop generation on transmit packets data and clock recovery from the usb serial stream bit stuffing and unstuffing; bit stuff error detection staging register to manage data rate variation due to bit stuffing and unstuffing 16-bit 30 mhz and 8-bit 60 mhz parallel interface ability to switch between fs and hs terminations and signaling supports detection of usb reset, suspend, and resume supports hs identification and dete ction as defined by the usb 2.0 specification supports transmission of resume signaling 3.3v operation two package options: 56-pin qfn and 56-pin vfbga all required terminations, including 1.5 kohm pull up on dplus, are internal to chip supports usb 2.0 test modes the cypress mobl-usb tx2 is a universal serial bus (usb) specification revision 2.0 transceiver, serial and deserializer, to a parallel interface of either 16 bits at 30 mhz or eight bits at 60 mhz. the mobl-usb tx2 provides a high speed physical layer interface that operates at the maximum allowable usb 2.0 bandwidth. this enables the system designer to keep the complex high speed analog usb components external to the digital asic. this decreases development time and associated risk. a standard usb 2.0-certifie d interface is provided and is compliant with transceiver macrocell interface (utmi) specifi- cation version 1.05 dated 3/29/2001. this product is also optimized to seamlessly interface with monahans -p & -l applications processors. it has been charac- terized by intel and is recommended as the usb 2.0 utmi trans- ceiver of choice for its monahans processors. it is also capable of tri-stating the utmi bus, wh ile suspended, to enable the bus to be shared with other devices. two packages are defined for the family: 56-pin qfn and 56-pin vfbga. the functional block diagram follows. tri_state logic block diagram [+] feedback
CY7C68000A document #: 38-08052 rev. *g page 2 of 15 applications mobile applications smart phones pda phones gaming phones mp3 players portable media players (pmp) gps tracking devices consumer applications cameras scanners dsl modems memory card readers non-consumer applications networking wireless lan home pna functional overview the functionality of this chip is described in the following sections: usb signaling speed the mobl-usb tx2 operates at two of the rates defined in the usb specification 2.0, dated 4/27/2000. full speed, with a signaling bit rate of 12 mbps high speed, with a signaling bit rate of 480 mbps the mobl-usb tx2 does not support the ls signaling rate of 1.5 mbps. transceiver clock frequency the mobl-usb tx2 has an on-chip oscillator circuit that uses an external 24 mhz (100 ppm) cr ystal with the following charac- teristics: parallel resonant fundamental mode 500 w drive level 27 to 33 pf (5% tolerance) load capacitors an on-chip phase-locked loop (pll) multiplies the 24 mhz oscil- lator up to 30 or 60 mhz, as required by the transceiver parallel data bus. the default utmi interface clock (clk) frequency is determined by the databus16_8 pin. buses the two packages enable a 8- or 16-bit bidirectional data bus for data transfers to a controlling unit. suspend and tri-state modes when the mobl-usb tx2 is not in use, the processor reduces power consumption by putting it into suspend mode using the suspend pin. while in suspend mode, tri-st ate mode may be enabled, which tri-states all outputs and ios, enabl ing the utmi interface pins to be shared with other devices. this is valuable in mobile handset applications, where gpios are at a premium. the outputs and ios are tri-stated ~50ns when tri-state mode is enabled, and are driven ~50ns when tri-state mode is disabled. all inputs must not be left floating while in tri-state mode. when resuming after a suspend, the pll stabilizes approxi- mately 200 s after the suspend pin goes high. reset pin an input pin (reset) resets the chip. this pin has hysteresis and is active high according to the utmi specification. the internal pll stabilizes approximately 200 s after v cc has reached 3.3v. line state the line state output pins linest ate[1:0] are driven by combina- tional logic and may be toggling between the ?j? and the ?k? states. they are synchronized to the clk signal for a valid signal. on the clk edge, the state of these lines reflect the state of the usb data lines. upon the clock edge the ?0? bit of the linestate pins is the state of the dplus line and the ?1? bit of linestate is the dminus line. when synchronized, the setup and hold timing of the linestate is identical to the parallel data bus. full-speed versus high-speed select the fs versus hs is done through the use of both xcvrselect and the termselect input signals. the termselect signal enables the 1.5 kohm pull up on to the dplus pin. when termselect is driven low, a se0 is asserted on the usb providing the hs termination and generating the hs idle state on the bus. the xcvrselect signal is the control that selects either the fs trans- ceivers or the hs transceivers. by setting this pin to a ?0? the hs transceivers are selected and by setting this bit to a?1? the fs transceivers are selected. [+] feedback
CY7C68000A document #: 38-08052 rev. *g page 3 of 15 operational modes the operational modes are cont rolled by the opmode signals. the opmode signals are capable of inhibiting normal operation of the transceiver and evoking special test modes. these modes take effect immediately and take precedence over any pending data operations. the transmission data rate when in opmode depends on the state of the xcvrselect input. mode 0 enables the transceiver to operate with normal usb data decoding and encoding. mode 1 enables the transceiver logic to support a soft disconnect feature that tri-states both the hs and fs transmitters, and removes any termination from the usb, making it appear to an upstream port that the device is disconnected from the bus. mode 2 disables bit stuff and nrzi encoding logic so ?1?s loaded from the data bus becomes ?j?s on the dplus/dminus lines and ?0?s become ?k?s. dplus/dminus impedance termination the CY7C68000A does not require external resistors for usb data line impedance termination or an external pull up resistor on the dplus line. these resistors are incorporated into the part. they are factory trimmed to meet the requirements of usb 2.0. incorporating these resistors also reduces the pin count on the part. opmode[1:0] mode description 00 0 normal operation 01 1 non-driving 10 2 disable bit stuffing and nrzi encoding 11 3 reserved [+] feedback
CY7C68000A document #: 38-08052 rev. *g page 4 of 15 pin configurations the following pages illustrate the individual pin diagrams t hat are available in the 56-pi n qfn and 56-pin vfbga packages. the packages offered use either an 8-bit (6 0 mhz) or 16-bit (30 mhz) bus interface. figure 1. CY7C68000A 56-pin qfn pin assignment d4 d3 v cc d2 reserved d1 d0 clk databus16_8 uni_bidi gnd txvalid v cc validh 28 27 26 25 24 23 22 21 20 19 18 17 16 15 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29 gnd d5 reserved d6 d7 d8 d9 reserved d10 d11 v cc d12 gnd d13 txready suspend reset av cc xtalout xtalin agnd av cc dplus dminus agnd xcvrselect termselect opmode0 v cc d14 d15 reserved tri_state rxerror rxactive rxvalid gnd linestate1 linestate0 v cc gnd opmode1 CY7C68000A 56-pin qfn [+] feedback
CY7C68000A document #: 38-08052 rev. *g page 5 of 15 figure 2. CY7C68000A 56- pin vfbga pin assignment 12345678 a b c d e f g h 1a 2a 3a 4a 5a 6a 7a 8a 1b 2b 3b 4b 5b 6b 7b 8b 1c 2c 3c 4c 5c 6c 7c 8c 1d 2d 7d 8d 1e 2e 7e 8e 1f 2f 3f 4f 5f 6f 7f 8f 1g 2g 3g 4g 5g 6g 7g 8g 1h 2h 3h 4h 5h 6h 7h 8h [+] feedback
CY7C68000A document #: 38-08052 rev. *g page 6 of 15 pin descriptions table 1. pin descriptions qfn vfbga name type default description [1] 4h1avcc powern/a analog v cc this signal provides power to the analog section of the chip. 8h5avcc powern/a analog v cc this signal provides power to the analog section of the chip. 7h4agnd powern/a analog ground connect to ground with as short a path as possible. 11 h8 agnd power n/a analog ground connect to ground with as short a path as possible. 9 h6 dplus i/o/z z usb dplus signal connect to the usb dplus signal. 10 h7 dminus i/o/z z usb dminus signal connect to the usb dminus signal. 49 g8 d0 i/o bidirectional data bus this bidirectional bus is used as the entire data bus in the 8-bit bidirectional mode or the least significant eight bits in the 16-bit mode. under the 8-bit unidirect ional mode, these bits are used as inputs for data, selected by the rxvalid signal. 48 g7 d1 i/o 46 g5 d2 i/o 44 g3 d3 i/o 43 g2 d4 i/o 41 f8 d5 i/o 39 f6 d6 i/o 38 f5 d7 i/o 37 f4 d8 i/o bidirectional data bus this bidirectional bus is used as the upper eight bits of the data bus when in the 16-bit mode, and not used when in the 8-bit bidirectional mode. under the 8-bit unidirectional mode these bits are used as outputs for data, selected by the txvalid signal. 36 f3 d9 i/o 34 f1 d10 i/o 33 g4 d11 i/o 31 e1 d12 i/o 29 d8 d13 i/o 27 g1 d14 i/o 26 e2 d15 i/o 50 a1 clk output clock this output is used for clocking the receive and transmit parallel data on the d[15:0] bus. 3 b2 reset input n/a active high reset resets the entire chip. this pin can be tied to v cc through a 0.1- f capacitor and to gnd through a 100 k resistor for a 10-ms rc time constant. 12 b3 xcvrselect input n/a transceiver select this signal selects between the full speed (fs) and the high speed (hs) transceivers: 0: hs transceiver enabled 1: fs transceiver enabled 13 b4 termselect input n/a termination select this signal selects between the full speed (fs) and the high speed (hs) terminations: 0: hs termination 1: fs termination 2 b1 suspend input n/a suspend places the CY7C68000A in a mode that draws minimal power from supplies. shuts do wn all blocks not necessa ry for suspend/resume operations. while suspended, termselect must always be in fs mode to ensure that the 1.5 kohm pull up on dplus remains powered. 0: CY7C68000A circuitry drawing suspend current 1: CY7C68000A circuitry drawing normal current note 1. unused inputs should not be left floating. tie either high or low as appropriate. outputs that are three-statable should only be pulled up or down to ensure signals at power-up and in standby. [+] feedback
CY7C68000A document #: 38-08052 rev. *g page 7 of 15 24 b8 tri_state input tri-state mode enable places the CY7C68000A into tri-state mode which tri-states all outputs and ios. tri-state mode can only be enabled while suspended. 0: disables tri-state mode 1: enables tri-state mode 19 c2 linestate1 output line state these signals reflect the current state of the single-ended receivers. they are combinatorial un til a ?usable? clk is available then they are synchronized to clk. they dire ctly reflect the current state of the dplus (linestate0) and dminus (linestate1). d? d+ description 0 0 0: se0 0 1 1: ?j? state 1 0 2: ?k? state 1 1 3: se1 18 c1 linestate0 output line state these signals reflect the current state of the single-ended receivers. they are combinatorial unti l a ?usable? clk is available then they are synchronized to clk. they dire ctly reflect the current state of the dplus (linestate0) and dminus (linestate1). d? d+ description 00?0: se0 01?1: ?j? state 10?2: ?k? state 11?3: se1 15 b6 opmode1 input operational mode these signals select among various operational modes. 10 description 00?0: normal operation 01?1: non-driving 10?2: disable bit stuffing and nrzi encoding 11?3: reserved 14 b5 opmode0 input operational mode these signals select among various operational modes. 10 description 00?0: normal operation 01?1: non-driving 10?2: disable bit stuffing and nrzi encoding 11?3: reserved 54 a5 txvalid input transmit valid this signal indicates that the data bus is valid. the asser- tion of transmit valid initiates sync on the usb. the negation of trans- mit valid initiates eop on the usb. t he start of sync must be initiated on the usb no less than one or no more that two clks after the assertion of txvalid. in hs (xcvrselect = 0) mode, the sync pattern must be asserted on the usb between 8- and 16-bit times after the assertion of txvalid is detected by the transmit state machine. in fs (xcvr = 1), the sync pattern must be asserted on the usb no less than one or more than two clks after the assertion of txvalid is detected by the transmit state machine. 1 a8 txready output transmit data ready if txvalid is asserted, the sie must always have data available for clocking in to the tx holding register on the rising edge of clk. if txvalid is true and txready is asserted at the rising edge of clk, the CY7C68000A loads the data on the data bus into the tx holding register on the next rising edge of clk. at that time, the sie should immediately present the data for the next transfer on the data bus . table 1. pin descriptions (continued) qfn vfbga name type default description [1] (continued) [+] feedback
CY7C68000A document #: 38-08052 rev. *g page 8 of 15 21 a4 rxvalid output receive data valid this signal indicates that the dataout bus has valid data. the receive data holding register is full and ready to be unloaded. the sie is expected to latch the dataout bus on the clock edge. 22 b7 rxactive output receive active this signal indicates that the receive state machine has detected sync and is active. rxactive is negated after a bit st uff error or an eop is detected. 23 a6 rxerror output receive error 0 indicates no error. 1 indicates that a receive error has been detected. 56 a7 validh i/o validh this signal indicates that the high-o rder eight bits of a 16-bit data word presented on the data bus are valid. when databus16_8 = 1 and txvalid = 0, validh is an output, indicating that the high-order receive data byte on the data bus is valid. when databus16_8 = 1 and txvalid = 1, validh is an input and indicates that t he high-order transmit data byte, presented on the data bus by the transceiver, is valid. when databus16_8 = 0, validh is undefined. the status of the receive low-order data byte is determined by rxvalid and are present on d0?d7. 51 a2 databus16_8 input data bus 16_8 this signal selects between 8- and 16-bit data transfers. 1?16-bit data path operation enabled. clk = 30 mhz. 0?8-bit data path operation enabled. w hen uni_bidi = 0, d[8:15] are un- defined. when uni_bidi =1, d[0:7] ar e valid on txvalid and d[8:15] are valid on rxvalid. clk = 60 mhz note: databus16_8 is static after power-on reset (por) and is only sampled at the end of reset. 6 h3 xtalin input n/a crystal input connect this signal to a 24 mhz parallel-resonant, funda- mental mode crystal and 30 pf capacitor to gnd. it is also correct to drive xtalin with an external 24 mhz square wave derived from another clock source. 5 h2 xtalout output n/a crystal output connect this signal to a 24 mhz parallel-resonant, funda- mental mode crystal and 30 pf (nominal) capacitor to gnd. if an external clock is used to drive xtalin, leave this pin open. 52 a3 uni_bidi input driving this pin high enables the unidirectional mode when the 8-bit interface is selected . uni_bidi is static af ter power-on reset (por). 55 c6 v cc power v cc . connect to 3.3v power source. 17 c7 v cc power n/a v cc . connect to 3.3v power source. 28 d7 v cc power n/a v cc . connect to 3.3v power source. 32 e7 v cc power n/a v cc . connect to 3.3v power source. 45 e8 v cc power n/a v cc . connect to 3.3v power source. 53 c4 gnd ground n/a ground. 16 c5 gnd ground n/a ground. 20 c3 gnd ground n/a ground. 30 d1 gnd ground n/a ground. 42 d2 gnd ground n/a ground. 47 g6 reserved input connect pin to ground. 40 f7 reserved input connect pin to ground. 35 f2 reserved input connect pin to ground. 25 c8 reserved input connect pin to ground. table 1. pin descriptions (continued) qfn vfbga name type default description [1] (continued) [+] feedback
CY7C68000A document #: 38-08052 rev. *g page 9 of 15 absolute maximum ratings storage temperature ................ .............. ... ?65c to +150c ambient temperature with power supplied ..... 0c to +70c supply voltage to ground potentia l ...............?0.5v to +4.0v dc input voltage to any input pin ............................. 5.25 v dc voltage applied to outputs in high-z state ................. .................... ?0.5v to v cc + 0.5v power dissipation .... ................................................ 630 mw static discharge voltage ........ ........... ........... ............ > 2000v max output current, per io pin ................................... 4 ma max output current, all 21?io pins ............................ 84 ma operating conditions t a (ambient temperature under bias) ............ 0c to +70c supply voltage ...............................................+3.0v to +3.6v ground voltage ................................................................. 0v f osc (oscillator or crystal frequency) ... 24 mhz 100 ppm ................................................................... parallel resonant dc characteristics table 2. dc characteristics parameter description conditions min typ max unit v cc supply voltage 3.0 3.3 3.6 v v ih input high voltage 2 5.25 v v il input low voltage ?0.5 0.8 v i i input leakage current 0< v in < v cc 10 a v oh output voltage high i out = 4 ma 2.4 v v ol output low voltage i out = ?4 ma 0.4 v i oh output current high 4ma i ol output current low 4ma c in input pin capacitance except dplus/dminus/clk 10 pf dplus/dminus/clk 15 pf c load maximum output capacitance output pins 30 pf i susp suspend current connected [2] 228 273 a disconnected [2] 835 a i cc supply current hs mode normal operation opmod[1:0] = 00 175 ma i cc supply current fs mode normal operation opmod[1:0] = 00 90 ma t reset minimum reset time 1.9 ms note 2. connected to the usb includes 1.5 kohm internal pull up. disconnected has the 1.5 kohm internal pull up excluded. [+] feedback
CY7C68000A document #: 38-08052 rev. *g page 10 of 15 ac electrical characteristics usb 2.0 transceiver usb 2.0-compliant in fs and hs modes. timing diagram hs/fs interface timing - 60 mhz figure 3. 60 mhz interface timing constraints table 3. 60 mhz interface timing constraints parameters parameter description min typ max unit notes t csu_min minimum setup time for txvalid 4 ns t ch_min minimum hold time for txvalid 1 ns t dsu_min minimum setup time for data (transmit direction) 4 ns t dh_min minimum hold time for data (transmit direction) 1 ns t cco clock to control out time for txready, rxvalid, rxactive and rxerror 18ns t cdo clock to data out time (receive direction) 1 8 ns tcsu_min tch_min tdsu_min tdh_min tcdo tcco datain dataout control_out control_in clk [+] feedback
CY7C68000A document #: 38-08052 rev. *g page 11 of 15 hs/fs interface timing - 30 mhz figure 4. 30 mhz timing interface timing constraints figure 5. tri-state mode timing constraints table 5. tri-state mode timing constraints parameters table 4. 30 mhz timing interf ace timing constraints parameters parameter description min typ max unit notes t csu_min minimum setup time for txvalid 16 ns t ch_min minimum hold time for txvalid 1 ns t dsu_min minimum setup time for data (transmit direction) 16 ns t dh_min minimum hold time for data (transmit direction) 1 ns t cco clock to control out time for txready, rxvalid, rxactive and rxerror 120ns t cdo clock to data out time (receive direction) 1 20 ns t vsu_min minimum setup time for valid h (transmit direction) 16 ns t vh_min minimum hold time for vali dh (transmit direction) 1 ns t cvo clock to validh out time (receive direction) 1 20 ns parameter description min typ max unit notes t tssu minimum setup time for tri-state 0 ns t tspd propagation delay for tri-state mode 50 ns tcsu_min tch_min tdsu_min tdh_min tcvo tcco datain dataout control_out control_in clk tcdo tvsu_min tvh_min ttssu ttspd ttspd suspend tri-state output / io xxxx hi-z [+] feedback
CY7C68000A document #: 38-08052 rev. *g page 12 of 15 ordering information ordering code package type CY7C68000A-56lfxc 56 qfn CY7C68000A-56baxc 56 vfbga cy3683 mobl-usb tx2 development board package diagrams the mobl-usb tx2 is available in two packages: 56-pin qfn 56-pin vfbga figure 6. 56-pin quad flatpack no lead package 8 x 8 mm (sawn version) ls56b 51-85187 *c [+] feedback
CY7C68000A document #: 38-08052 rev. *g page 13 of 15 pcb layout recommendations follow these recommendations to ensure reliable, high-perfor- mance operation [3] . a four-layer impedance controlled board is required to maintain signal quality specify impedance targets (ask your board vendor what they can achieve) to control impedance, maintain trace widths and trace spacing to within writte n specifications minimize stubs to minimize reflected signals connections between the usb connector shell and signal ground must be done near the usb connector bypass and flyback capacitors on vbus, near the connector, are recommended keep dplus and dminus trace lengths within 2 mm of each other in length, with preferred length of 20 to 30 mm maintain a solid ground plane under the dplus and dminus traces. do not split the plane under these traces do not place vias on the dplus or dminus trace routing isolate the dplus and dminus tr aces from all other signal traces by no less than 10 mm package diagrams (continued) figure 7. 56 vfbga (5 x 5 x 1.0 mm) 0.50 pitch, 0.30 ball bz56 top view pin a1 corner 0.50 3.50 5.000.10 bottom view 0.10(4x) 3.50 5.000.10 0.50 ?0.15 m c a b ?0.05 m c ?0.300.05(56x) a1 corner -b- -a- 1.0 max 0.160 ~0.260 0.080 c 0.45 seating plane 0.21 0.10 c -c- side view 5.000.10 5.000.10 reference jedec: mo-195c package weight: 0.02 grams e g h f d c b a 13 26 5 48 6 7 85 6 2 3 41 e g h f d c b a 001-03901-*b note 3. source for recommendations: ez-usb fx2? pcb design recommendations , http:///www.cypress.com/cfuploads/support/app_notes/fx2_pcb.pdf high-speed usb platform design guidelines , http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf. [+] feedback
CY7C68000A document #: 38-08052 rev. *g page 14 of 15 quad flat package no leads (qfn) package design notes electrical contact of the part to the printed circuit board (pcb) is made by soldering the leads on the bottom surface of the package to the pcb. hence, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. a copper (cu) fill is to be designed into the pcb as a thermal pad under the package. heat is transferred from the mobl-usb tx2 through the device?s metal paddle on the package bottom. from here, he at is conducted to the pcb at the thermal pad. it is then condu cted from the thermal pad to the pcb inner ground plane by an array of via. a via is a plated through-hole in the pcb with a finished diameter of 13 mil. the qfn?s metal die paddle must be soldered to the pcb?s thermal pad. solder mask is placed on th e board top, over each via, to resist solder flow into the via. the mask on the top side also minimizes outgassing during the solder reflow process. for further informa tion on this package design, refer to the appli- cation note ?surface mount assembly of amkor?s microlead- frame (mlf) technology.? download this application note from amkor?s website, by following this link: http://www.amkor.com/products/notes_papers/mlfapp note.pdf . the application note provides detailed information on board mounting guidelines, soldering flow, and rework process. figure 8 displays a cross-sectional area under the package. the cross section is of only one via. the solder paste template needs to be designed to enable at least 50 percent solder coverage. the thickness of the solder paste template should be 5 mil. it is recommended that ?no clean?, type 3 solder paste be used for mounting the part. nitrogen pu rge is recommended during reflow. figure 9 is a plot of the solder mask pattern image of the assembly (darker areas indicate solder). figure 9. plot of the solder mask (white area) figure 8. cross section of the area underneath the qfn package 0.017? dia solder mask cu fill cu fill pcb material pcb material 0.013? dia via hole for thermally connecting the qfn to the circuit board ground plane. this figure only shows the top three layers of the circuit board: top solder, pcb dielectric, and the ground plane [+] feedback
document #: 38-08052 rev. *g revi sed october 5, 2008 page 15 of 15 mobl-usb tx2 is a trademark of cypress semiconductor corporation. intel is a registered trademark of intel corporation. all pro duct and company names mentioned in this document are the trademarks of their respective holders. all products and company names mentioned in this document may be the trademarks of their respective holders. CY7C68000A ? cypress semiconductor corporation, 2004-2008. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document title: CY7C68000A mobl-u sb? tx2 usb 2.0 utmi transceiver document number: 38-08052 rev. ecn no. orig. of change submission date description of change ** 285592 kku see ecn new data sheet *a 427959 teh see ecn addition of vfbga package information and pinout, removal of ssop package. edited text and moved figure titles to the top per new template *b 470121 teh see ecn change from preliminary to final data sheet. grammatical and formatting changes *c 476107 teh see ecn this data sheet needs to be posted to the web site under nda *d 491668 teh see ecn addition of tri-state mode *e 498415 teh see ecn update power consumption numbers *f 567869 teh see ecn remove nda requirement *g 2587010 kku/pyrs 10/13/08 update pin 6 description on page 8 update template [+] feedback

▲Up To Search▲

Price & Availability of CY7C68000A

	To Download CY7C68000A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .